1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an SOI (Silicon on Insulator) structure.
2. Description of the Background Art
A dynamic random access memory (referred to as DRAM hereinafter) that allows random input and output of stored information is well known as a semiconductor device. A DRAM includes a memory cell array which is the memory region of storing information and a peripheral circuit required for input/output with respect to an external source.
An exemplary structure of a DRAM memory cell will be described hereinafter. FIG. 30 is a sectional view of a genal DRAM memory cell. This memory cell includes a typical stacked type capacitor.
Referring to FIG. 30, a memory cell includes one transfer gate transistor and one stacked type capacitor.
The transfer gate transistor includes a pair of source/drain regions 30, 30 formed on a surface of a silicon substrate 1, and a gate electrode (word line) 6 formed on the surface of silicon substrate 1 with an insulating layer therebetween.
The stacked type capacitor includes a lower electrode (storage node) 9 extending from over gate electrode 6 to a field isolation film 4, and having a portion thereof connected to one of source/drain regions 30, 30, a dielectric layer 901 formed on the surface of lower electrode 9, and an upper electrode (cell plate) 902 formed thereon.
A bit line 10 is connected to the other source/drain region 30 of the transfer gate transistor via a bit line contact unit 100.
In recent years, the technology of transistors using an SOI structure has evolved. Such a transistor of an SOI structure is characterized in that the operation of circuitry is speeded, according to reduction in the capacitance between the interconnection and the substrate, i.e. the wiring capacitance. When this transistor is applied to a CMOS, the latch up phenomenon can be prevented. There are also various advantages such as the short channel effect is reduced, the current driving capability and the subthreshold characteristics are improved.
Therefore, application of an SOI structure into a memory cell of a DRAM is considered.
However, in the stage of applying an SOI structure into a memory cell of a DRAM, the following problems were generated.
FIGS. 31A-31F are sectional views of a memory cell of an SOI structure showing the first to sixth manufacturing steps thereof for describing the problems encountered in the manufacturing process. The main steps of the manufacturing method of the present memory cell are shown.
Referring to FIG. 31A, a silicon substrate 1 is prepared. Oxygen ions are implanted from above silicon substrate 1 with silicon substrate 1 is heated to a predetermined temperature. Then, annealing is carried out at a high temperature.
As a result, silicon substrate 1 reacts with the oxygen ions, whereby an insulating layer 2 of silicon oxide (SiO.sub.2) is formed. The defects generated by oxygen ion implantation are eliminated, whereby the crystalline property thereof is recovered. As a result, a silicon layer of single crystalline (referred to as SIO layer hereinafter) 3 is formed.
Thus, an insulating layer 2 is located at the depth of 5000-10000 .ANG. from the top face of the original silicon substrate. On insulating layer 2, a first conductivity type SOI layer 3 having a thickness of approximately 1000 .ANG. is formed.
Then, a field oxide film 4 is formed on the main surface of silicon substrate 1.
Referring to FIG. 31B, the surface of SOI layer 3 is processed by thermal oxidation, whereby a gate oxide film 5 is formed on the surface of SOI layer 3. Gate oxide film 5 has a thickness of approximately 100 .ANG.. Here, the thickness of SOI layer 3 is reduced by the thickness of gate oxide film 5. Then, a gate electrode layer 60 of polysilicon is formed on gate oxide film 5.
Referring to FIG. 31C, using a resist pattern (not shown) formed on gate electrode layer 60 located above the center portion between field oxide films 4, 4 as a mask, gate electrode layer 60 and gate oxide film 5 are etched away to be patterned. By this patterning, gate electrode 6 is formed.
In this patterning step, SOI layer 3 beneath gate electrode layer 60 removed by etching is also removed due to that etching process.
Referring to FIG. 31D, ions are implanted into one of the pair of regions in SOI layer 3 sandwiching the region beneath gate electrode 6 between field insulating films 4, 4, whereby a first impurity region (drain region or source region) 31 of a second conductivity type is formed.
Then, an interlayer insulating layer 71 is formed so as to cover the surface of SOI layer 3, gate electrode 6, and field oxide films 4, 4. Interlayer insulating layer 71 on first impurity region 31 is removed by etching. As a result, a contact hole 71 is formed.
In this formation of contact hole 710, SOI layer 3 is removed by the influence of the etching process. Then, a bit line layer 100 of polysilicon is formed on the surface of interlayer insulating layer 71 so as to come into contact with SOI layer 3 through contact hole 710.
Referring to FIG. 31E, using a resist pattern (not shown) of a predetermined configuration as a mask, bit line layer 100 is etched away to be patterned. In this patterning process, interlayer insulating layer 71 on a region of SOI layer 3 located opposite to first impurity region 31 with the region beneath gate electrode 6 therebetween is removed by etching at the same time. This is because interlayer insulating layer 71 is etched easier than bit line layer 100 of polysilicon.
As interlayer insulating layer 71 is removed, the portion of SOI layer 3 beneath the removed interlayer insulating layer 71 is also exposed and removed.
Referring to FIG. 31F, ions are implanted into the exposed SOI layer 3, whereby an impurity region 32 of a second conductivity type is formed. Then, an interlayer insulating layer 72 is formed. Interlayer insulating layer 72 located on the region of SOI layer 3 opposite to first impurity region 31 with the region beneath gate electrode layer 6 therebetween is removed by etching to form a contact hole 720. In the formation of contact hole 720, SOI layer 3 is removed due to this etching process.
Then, a lower electrode layer is formed on the surface of interlayer insulating layer 72 so as to come into contact with SOI layer 3 through contact hole 720. The lower electrode layer is patterned, whereby a storage node (lower electrode) 9 is formed.
After this step of FIG. 31F, a dielectric layer and a cell plate (upper electrode) are sequentially formed on storage node 9.
When an SOI structure is applied to a DRAM memory cell, there was the problem that the thickness of SOI layer 3 is reduced in manufacturing a memory cell. In the worst case, a through hole in SOI layer 3 was generated. The reason why the thickness of SOI layer 3 is reduced is summarized as follows.
First, the thickness of SOI layer 3 is reduced due to the thermal oxidation process in forming gate oxide film 5. Then, SOI layer 3 is removed also in the patterning process of gate electrode layer 60. SOI layer 3 is also removed during formation of contact holes 710 and 720. Furthermore, SOI layer 3 is removed in patterning the conductive layer located right above the gate electrode such as bit line layer 100.
When this impurity region is to be formed as a LDD (Lightly Doped Drain) structure, SOI layer 3 is also removed in the etching process of the sidewall.
Thus, there was the problem that the thickness of the SOI layer is significantly removed during the manufacturing process in the case where an SOI structure is applied to a DRAM memory cell. This reduction causes various problems such as contact failure between the SOI layer and a conductive layer such as a storage node in contact thereto.
In a conventional semiconductor device wherein a source and a drain of a transistor formed on a silicon substrate are coupled to different layers, contact holes on the source and drain regions are generally formed through different steps. When forming such contact holes, oxide film portions on the source and drain regions are generally overetched to the extent to remove even the source and drain layers to different depths. FIG. 32 is a schematic diagram showing such situation where the source and drain layers are removed to different depths as a result of overetching. In FIG. 32, one source/drain layer 31 and another source/drain layer 32 formed in a substrate 1 and to be coupled to different layers 10 and 9 are overetched through different steps when forming the corresponding contact holes, resulting in a difference in film thickness between the source and drain sides. Such difference in film thickness causes a difference in resistance values of the source and drain, which difference deteriorates transistor characteristics. In case of a transistor formed on a SOI structure as shown in FIG. 33 where the insulating layer 2 is provided, especially, there is a possibility that one of the source/drain layers 31,32 may be removed to its entire depth due to overetching and electric contact to the source/drain of the transistor may not be formed.
More specifically, with reference to the steps of the conventional example shown in FIGS. 31A-31F, both source and drain regions are damaged when etching the gate electrode in the step shown in FIG. 31C (the first damage), and then only one source/drain region is further damaged when etching the first connecting layer in the step shown in FIG. 31E (the second damage). These damages caused by a different number of etching steps result in a difference in film thickness between the source and drain regions and unfavorable effects on transistor characteristics. In the case of an SOI structure, the one source/drain film subjected to etching damages twice might be fully removed and disappear.
The above-described status is encountered not only in a DRAM memory cell, but also in a general transistor. More specifically, it occurs in the case where the structure right above a source region differs from that right above a drain region in a pair of source/drain regions in a transistor. A typical example of a transistor of such a structure is a transistor of a DRAM memory cell.
The type of a conductive layer right above the source/drain region of a transistor differs depending upon the structure of the memory cell. Therefore, the above described problem also occurs in the case where the conductive layer right above the source/drain region of the transistor is a polypad, a storage node interconnection layer, or a bit line interconnection layer.
The above-described problem is not limited to a DRAM memory cell, and is seen also in a SRAM (problems identical to those in a DRAM memory cell occurs). Furthermore, the above-described problem occurs in a general CMOS circuit in which polypads are respectively formed at the power supply side and the ground side, and not formed at the signal output side, or vice versa.